Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Model checking
Symbolic Model Checking
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
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The application of formal methods to the logic verification of electronic circuits is meant for increasing the coverage obtained by the traditional verification techniques. This concept is quite popular in the design community but requires some guidelines in order to be implemented. The purpose of this work is to show that the advantage of Equivalence Checking and Model Checking, by far the two more important techniques in Logic Formal Verification, resides in the capability of powerful and concise modeling of the environment driving the verification process and in the capability of concise description of the expected behavior; such characteristics often achieve exhaustiveness which is difficult to reach with other verification techniques. A unified vision of environment modeling in the combinational and sequential worlds is proposed; results of application of the underlying ideas are reported on real industrial cases.