Symbolic simulation—techniques and applications

Authors:
Randal E. Bryant
Affiliations:
School of Computer Science, Carnegie Mellon University, Pittsburgh, PA
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 9
Cited 22

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
COSMOS: a compiled simulator for MOS circuits

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Test pattern generation for sequential MOS circuits by symbolic fault simulation

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Coded time-symbolic simulation using shared binary decision diagram

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computer Logic, Testing and Verification

Computer Logic, Testing and Verification
Symbolic simulation for functional verification with ADLIB and SDL

DAC '81 Proceedings of the 18th Design Automation Conference
Symbolic simulation for correct machine design

DAC '79 Proceedings of the 16th Design Automation Conference
The application of program verification techniques to hardware verification

DAC '79 Proceedings of the 16th Design Automation Conference

Formal verification of PowerPC arrays using symbolic trajectory evaluation

DAC '96 Proceedings of the 33rd annual Design Automation Conference
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs

ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Interface timing verification drives system design

DAC '97 Proceedings of the 34th annual Design Automation Conference
Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation

DAC '98 Proceedings of the 35th annual Design Automation Conference
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays

Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Probabilistic state space search

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays

Proceedings of the conference on Design, automation and test in Europe
Smart simulation using collaborative formal and simulation engines

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays

Journal of Electronic Testing: Theory and Applications
A symbolic simulation approach in resolving signals' correlation

SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)
Improved SAT-based Bounded Reachability Analysis

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
12.2 On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Validation Methodology Combining Test and Formal Verification For PowerPC" Microprocessor Arrays

ITC '97 Proceedings of the 1997 IEEE International Test Conference
Concrete Impact of Formal Verification on Quality in IP Design and Implementation

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Concurrent MIN-MAX simulation

EURO-DAC '91 Proceedings of the conference on European design automation
A Top-Down Methodology for Microprocessor Validation

IEEE Design & Test
Functional test generation based on word-level SAT

Journal of Systems Architecture: the EUROMICRO Journal
Efficient symbolic simulation of low level software

Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages

Processor Description Languages
Facilitating unreachable code diagnosis and debugging

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Verification of an error correcting code by abstract interpretation

VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a range of circuit operating conditions. In one simulation run, a symbolic simulator can compute what would require many runs of a traditional simulator. Symbolic simulation has applications in both logic and timing verification, as well as sequential test generation.The concept of symbolic simulation has been discussed for over 10 years, but early attempts had only limited success. The recent introduction of more powerful, algorithmic methods of symbolic manipulation have had a major impact on the classes of circuits and properties that can be evaluated symbolically.