Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Design validation for embedded arrays remains as a challenging problemin today‘s microprocessor design environment. Although several methods for validating embedded arrayshave been proposed, notmuch has beendone to characterize the strengths and weaknesses of these methods.This paper provides a comprehensive study of various design validation approaches adopted at the Somerset PowerPC Design Center in the past, including methodsfrom both formal verification and test generation.Effectiveness of these approaches will be measured based onautomatic design error injection and simulation at both gate and transistor levels. Experience ofusing different validation approaches on recent PowerPC microprocessor arrays will be analyzed and discussed.