Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Journal of Electronic Testing: Theory and Applications
MODELING AND TESTING THE GEKKO MICROPROCESSOR, AN IBM POWERPC DERIVATIVE FOR NINTENDO
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design-For-Test Methodology for Motorola PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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Test and validation of embedded array blocks remains a majorchallenge in today‘s microprocessor design environment. The difficulty comesfrom twofold, the sizes of the arrays and the complexity of theirtiming and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays.Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shownthrough various experiments on recent PowerPC microprocessor designs.