Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
A methodology for formal hardware verification, with application to microprocessors
A methodology for formal hardware verification, with application to microprocessors
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
DAC '98 Proceedings of the 35th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Journal of Electronic Testing: Theory and Applications
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design for Verification at the Register Transfer Level
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Formal Methods in System Design
Automated Analysis of Reo Circuits using Symbolic Execution
Electronic Notes in Theoretical Computer Science (ENTCS)
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Efficient automatic STE refinement using responsibility
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Selective state retention design using symbolic simulation
Proceedings of the Conference on Design, Automation and Test in Europe
A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL
Theoretical Computer Science
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
An introduction to symbolic trajectory evaluation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Symbolic execution of Reo circuits using constraint automata
Science of Computer Programming
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In this paper we report on new techniques for verifying contentaddressable memories (CAMs), and demonstrate that these techniqueswork well for large industrial designs. It was shown in [Formal verification of PowerPC(TM) arrays using symbolic trajectory evaluation], that theformal verification technique of symbolic trajectory evaluation (STE)could be used successfully on memory arrays. We have extended thatwork to verify what are perhaps the most combinatorially difficultclass of memory arrays, CAMs. We use new Boolean encodings toverify CAMs, and show that these techniques scale well, in that spacerequirements increase linearly, or sub-linearly, with the various CAMsize parameters.In this paper, we describe the verification of two CAMs froma recentPowerPC驴 microprocessor design, a Block Address Translation unit(BAT), and a Branch Target Address Cache unit (BTAC). The BATis a complex CAM, with variable length bit masks. The BTAC is a64-entry, 64-bits per entry, fully associative CAM and is part of thespeculative instruction fetch mechanism of the microprocessor. Webelieve that ours is the first work on formally verifying CAMs, and webelieve our techniques make it feasible to efficiently verify the varietyof CAMs found on modern processors.