Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Explaining symbolic trajectory evaluation by giving it a faithful semantics
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation
Proceedings of the 45th annual Design Automation Conference
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Efficient automatic STE refinement using responsibility
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Software model checking via IC3
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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We present a SAT-based algorithm for assisting users of Symbolic Trajectory Evaluation (STE) in manual abstraction refinement. As a case study, we demonstrate the usefulness of the algorithm by showing how to refine and verify an STE specification of a CAM.