Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
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FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
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TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
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ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
CSCWD'06 Proceedings of the 10th international conference on Computer supported cooperative work in design III
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
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CSR'06 Proceedings of the First international computer science conference on Theory and Applications
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CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
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SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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We present a new SAT-based algorithm for Symbolic Trajectory Evaluation (STE), and compare it to more established SAT-based techniques for STE.