Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Model checking
Symbolic Model Checking
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Formal Verification Methods for Industrial Hardware Design
SOFSEM '01 Proceedings of the 28th Conference on Current Trends in Theory and Practice of Informatics Piestany: Theory and Practice of Informatics
Model Checking Linear Properties of Prefix-Recognizable Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
An automata-theoretic approach to infinite-state systems
Time for verification
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Minimizing generalized büchi automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
An introduction to symbolic trajectory evaluation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Deterministic dynamic monitors for linear-time assertions
FATES'06/RV'06 Proceedings of the First combined international conference on Formal Approaches to Software Testing and Runtime Verification
The Multivariate Algorithmic Revolution and Beyond
Complete SAT solver based on set theory
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
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We describe the techniques we have used to search for bugs in the memory subsystem of a next-generation Alpha microprocessor. Our approach is based on two model checking methods that use satisfiability (SAT) solvers rather than binary decision diagrams (BDDs). We show that the first method, bounded model checking, can reduce the verification runtime from days to minutes on real, deep, microprocessor bugs when compared to a state-of-the-art BDD-based model checker. We also present experimental results showing that the second method, a version of symbolic trajectory evaluation that uses SAT-solvers instead of BDDs, can find as deep bugs, with even shorter runtimes. The tradeoff is that we have to spend more time writing specifications. Finally, we present our experiences with the two SAT-solvers that we have used, and give guidelines for applying a combination of bounded model checking and symbolic trajectory evaluation to industrial strength verification. The bugs we have found are significantly more complex than those previously found with methods based on SAT-solvers.