Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
The Industrial Success of Verification Tools Based on Stålmarck's Method
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The Semantics of Verilog Using Transition System Combinators
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Satisfiability Checking Using Boolean Expression Diagrams
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Saturation: An Efficient Iteration Strategy for Symbolic State-Space Generation
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Improving the Encoding of LTL Model Checking into SAT
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Integrating BDD-Based and SAT-Based Symbolic Model Checking
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ATPG-based preimage computation: efficient search space pruning with ZBDD
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
New Encodings of Pseudo-Boolean Constraints into CNF
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Faster SAT solving with better CNF generation
Proceedings of the Conference on Design, Automation and Test in Europe
Incremental compilation-to-SAT procedures
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Clause form conversions for boolean circuits
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
Saturation-based symbolic reachability analysis using conjunctive and disjunctive partitioning
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Improvements to the implementation of interpolant-based model checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Symbolic model checking for temporal-epistemic logic
Logic Programs, Norms and Action
SAT-Based bounded model checking for deontic interleaved interpreted systems
KES-AMSTA'12 Proceedings of the 6th KES international conference on Agent and Multi-Agent Systems: technologies and applications
BDD-based Bounded Model Checking for Temporal Properties of 1-Safe Petri Nets
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Incremental, inductive CTL model checking
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
SAT-based Unbounded Model Checking of Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
Towards SAT-based BMC for LTLK over Interleaved Interpreted Systems
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Growing solver-aided languages with rosette
Proceedings of the 2013 ACM international symposium on New ideas, new paradigms, and reflections on programming & software
Autonomous Agents and Multi-Agent Systems
A New Translation from ECTL* to SAT
Fundamenta Informaticae - Concurrency Specification and Programming CS&P
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The introduction of symbolic model checking using Binary Decision Diagrams (BDDs) has led to a substantial extension of the class of systems that can be algorithmically verified. Although BDDs have played a crucial role in this success, they have some well-known drawbacks, such as requiring an externally supplied variable ordering and causing space blowups in certain applications. In a parallel development, SAT-solving procedures, such as Stålmarck's method or the Davis-Putnam procedure, have been used successfully in verifying very large industrial systems. These efforts have recently attracted the attention of the model checking community resulting in the notion of bounded model checking. In this paper, we show how to adapt standard algorithms for symbolic reachability analysis to work with SAT-solvers. The key element of our contribution is the combination of an algorithm that removes quantifiers over propositional variables and a simple representation that allows reuse of subformulas. The result will in principle allow many existing BDD-based algorithms to work with SAT-solvers. We show that even with our relatively simple techniques it is possible to verify systems that are known to be hard for BDD-based model checkers.