MDG-SAT: an automated methodology for efficient safety checking

Authors:
Khaza Anuarul Hoque;Otmane Ait Mohamed; Sa';ed Abed;Mounir Boukadoum
Affiliations:
Department of Electrical and Computer Engineering, Concordia University, 1455 de Maisooneve Blvd. W, Montreal, Quebec H3G 1M8, Canada.;Department of Electrical and Computer Engineering, Concordia University, 1455 de Maisooneve Blvd. W, Montreal, Quebec H3G 1M8, Canada.;Department of Computer Engineering, Hashemite University, P.O. Box 150459, Zarqa 13115, Jordan.;Department of Computer Science, University of Quebec at Montreal, CP. 8888, Succ. Centre-Ville, Montreal, QC H3P 3P8, Canada;-
Venue:
International Journal of Critical Computer-Based Systems
Year:
2012

Citing 23
Cited 0

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Introduction to HOL: a theorem proving environment for higher order logic

Introduction to HOL: a theorem proving environment for higher order logic
GRASP—a new search algorithm for satisfiability

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Computing Procedure for Quantification Theory

Journal of the ACM (JACM)
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic (TOCL)
Chaff: engineering an efficient SAT solver

Proceedings of the 38th annual Design Automation Conference
Multiway Decision Graphs for Automated Hardware Verification

Formal Methods in System Design
SAT-Based Image Computation with Application in Reachability Analysis

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Reachability Analysis Based on SAT-Solvers

TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Using induction and BDDs to model check invariants

Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Pruning Techniques for the SAT-Based Bounded Model Checking Problem

CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SATO: An Efficient Propositional Prover

CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Learning from BDDs in SAT-based bounded model checking

Proceedings of the 40th annual Design Automation Conference
On the non-termination of MDG-based abstract state enumeration

Theoretical Computer Science
Improved SAT-based Bounded Reachability Analysis

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient translation of boolean formulas to CNF in formal verification of microprocessors

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Completeness in SMT-based BMC for software programs

Proceedings of the conference on Design, automation and test in Europe
An abstraction-based decision procedure for bit-vector arithmetic

International Journal on Software Tools for Technology Transfer (STTT)
The verification of mdg algorithms in the hol theorem prover

The verification of mdg algorithms in the hol theorem prover
An abstract reachability approach by combining HOL induction and multiway decision graphs

Journal of Computer Science and Technology
Applying logic synthesis for speeding up SAT

SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
Faster SAT solving with better CNF generation

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multiway decision graph (MDG) is a canonical representation of a subset of many-sorted first-order logic. It generalises the logic of equality with abstract types and uninterpreted function symbols. The area of satisfiability (SAT) has been the subject of intensive research in recent years, with significant theoretical and practical contributions. In this paper, we propose a new design verification tool integrating MDG and SAT, to check the safety of a design by invariant checking. Using MDG to encode the set of states provides a powerful mean of abstraction. We use a SAT solver to search for paths of reachable states violating the property under certain encoding constraints. In addition, we introduce an automated conversion-verification methodology to convert a directed formula (DF) into a conjunctive normal form (CNF) formula that can be fed to a SAT solver. The formal verification of this conversion is conducted within the HOL theorem prover. Finally, we present experimental results and a case study to show the correctness and the efficiency of our proposed methodology.