Symbolic Model Checking
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Verification of Embedded Software: Problems and Perspectives
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
SAT-Based Scalable Formal Verification Solutions (Series on Integrated Circuits and Systems)
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Bounded model checking of software using SMT solvers instead of SAT solvers
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Efficient Modeling of Concurrent Systems in BMC
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
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Bounded Model Checking (BMC) is incomplete without a completeness threshold (CT) bound. Previous methods, using recurrence diameter for obtaining CT, check for existence of a longest loop-free path at every depth k. For terminating software programs, we propose an efficient method for obtaining CT that requires solving a formula of size O(k) at some depths only, as compared to previous methods that require solving a formula of O(k2) (or O(klogk)) size at every depth. We augment previous methods for BMC simplifications using model transformation and control flow information, with context-sensitive analysis. This results in more BMC simplifications and further reduction in the number of CT checks. We have implemented our techniques in a Satisfiability Modulo Theory (SMT)-based BMC framework. Our controlled experiments on real-world software programs show that our proposed formulation provides significant improvements over previous approaches.