A Parallelization Scheme Based on Work Stealing for a Class of SAT Solvers
Journal of Automated Reasoning
Efficient distributed SAT and SAT-based distributed Bounded Model Checking
International Journal on Software Tools for Technology Transfer (STTT) - A View from Formal Methods 2003 (pp 301-354); Special Section on Recent Advances in Hardware Verification (pp 355-447)
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exploring Clause Symmetry in a Distributed Bounded Model Checking Algorithm
ECBS '07 Proceedings of the 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems
Tunneling and slicing: towards scalable BMC
Proceedings of the 45th annual Design Automation Conference
Completeness in SMT-based BMC for software programs
Proceedings of the conference on Design, automation and test in Europe
Parallel SAT solving in bounded model checking
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
F-SOFT: software verification platform
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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We present a tool d-TSR for parallelizing SMT-based BMC over a distributed environment targeted for checking safety properties in low-level embedded (sequential) software. We use a tunneling and slicing-based reduction (TSR) approach to decompose disjunctively a BMC instance (at a given depth) into simpler and independent subproblems. We exploit such a decomposition to cut down communication cost and idle time of CPUs during synchronization while solving BMC instances. Our approach scales almost linearly with number of CPUs, as demonstrated in our experimental results.