Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Using induction and BDDs to model check invariants
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal verification of the FPGA cores
Nordic Journal of Computing
An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
CP '02 Proceedings of the 8th International Conference on Principles and Practice of Constraint Programming
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Conflict driven learning in a quantified Boolean Satisfiability solver
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Checking reachability properties for timed automata via SAT
Fundamenta Informaticae - Concurrency specification and programming
Enhanced Diameter Bounding via Structural
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Iterative Abstraction using SAT-based BMC with Proof Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Exploiting state encoding for invariant generation in induction-based property checking
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Defining and translating a "safe" subset of simulink/stateflow into lustre
Proceedings of the 4th ACM international conference on Embedded software
Using RTL Statespace Information and State Encoding for Induction Based Property Checking
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proof-guided underapproximation-widening for multi-process systems
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Principles of Sequential-Equivalence Verification
IEEE Design & Test
Model Checking C Programs Using F-SOFT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
State Set Management for SAT-based Unbounded Model Checking
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Temporal Decomposition for Logic Optimization
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient computation of small abstraction refinements
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT-based sequential depth computation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automatic assume guarantee analysis for assertion-based formal verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
HW/SW co-verification of embedded systems using bounded model checking
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast illegal state identification for improving SAT-based induction
Proceedings of the 43rd annual Design Automation Conference
Automatic invariant strengthening to prove properties in bounded model checking
Proceedings of the 43rd annual Design Automation Conference
Planning as satisfiability: parallel plans and algorithms for plan search
Artificial Intelligence
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Bounded model checking of infinite state systems
Formal Methods in System Design
Stepping forward with interpolants in unbounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interpolant Learning and Reuse in SAT-Based Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Compressing BMC Encodings with QBF
Electronic Notes in Theoretical Computer Science (ENTCS)
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the the 6th joint meeting of the European software engineering conference and the ACM SIGSOFT symposium on The foundations of software engineering
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simulation-directed invariant mining for software verification
Proceedings of the conference on Design, automation and test in Europe
Completeness in SMT-based BMC for software programs
Proceedings of the conference on Design, automation and test in Europe
Model checking with Boolean Satisfiability
Journal of Algorithms
Efficient SAT-based bounded model checking for software verification
Theoretical Computer Science
A Symbolic Model Checking Framework for Safety Analysis, Diagnosis, and Synthesis
Model Checking and Artificial Intelligence
Tutorial on Model Checking: Modelling and Verification in Computer Science
AB '08 Proceedings of the 3rd international conference on Algebraic Biology
Benchmarking Model- and Satisfiability-Checking on Bi-infinite Time
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
Encoding Queues in Satisfiability Modulo Theories Based Bounded Model Checking
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Automated abstraction by incremental refinement in interpolant-based model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
BTOR: bit-precise modelling of word-level problems for model checking
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Scaling up the formal verification of Lustre programs with SMT-based techniques
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Consistency checking of all different constraints over bit-vectors within a SAT solver
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Comparison of Maude and SAL by Conducting Case Studies Model Checking a Distributed Algorithm
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Enhancing SAT-based sequential depth computation by pruning search space
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Specification and verification of time requirements with CCSL and Esterel
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
On Extending Bounded Proofs to Inductive Proofs
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Automated deduction for verification
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Model checking: algorithmic verification and debugging
Communications of the ACM - Scratch Programming for All
The dependence condition graph: Precise conditions for dependence between program points
Computer Languages, Systems and Structures
Diagnosability testing with satisfiability algorithms
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Discrete Event Dynamic Systems
Planning as satisfiability: parallel plans and algorithms for plan search
Artificial Intelligence
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abstract Model Checking without Computing the Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Safety Property Verification of Cyclic Synchronous Circuits
Electronic Notes in Theoretical Computer Science (ENTCS)
SAT-based Induction for Temporal Safety Properties
Electronic Notes in Theoretical Computer Science (ENTCS)
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Using Satisfiability Modulo Theories for Inductive Verification of Lustre Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Computing Over-Approximations with Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Termination Criteria for Bounded Model Checking: Extensions and Comparison
Electronic Notes in Theoretical Computer Science (ENTCS)
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Proving unreachability using bounded model checking
Proceedings of the 3rd India software engineering conference
SAT-based verification of LTL formulas
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Verification of data paths using unbounded integers: automata strike back
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Bounded model checking for past LTL
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A SAT characterization of boolean-program correctness
SPIN'03 Proceedings of the 10th international conference on Model checking software
SAT-based compositional verification using lazy learning
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Guiding the correction of parameterized specifications
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Model checking with SAT-based characterization of ACTL formulas
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
Verification of ACTL properties by bounded model checking
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Approximation refinement for interpolation-based model checking
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analyzing k-step induction to compute invariants for SAT-based property checking
Proceedings of the 47th Design Automation Conference
Medical cyber physical systems
Proceedings of the 47th Design Automation Conference
SMT-AI: an Abstract Interpreter as Oracle for k-induction
Electronic Notes in Theoretical Computer Science (ENTCS)
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Combinatorial Optimization Solutions for the Maximum Quartet Consistency Problem
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Logical time: specification vs. implementation
ACM SIGSOFT Software Engineering Notes
Handling State-Machines Specifications with GATeL
Electronic Notes in Theoretical Computer Science (ENTCS)
Mutation-based test case generation for simulink models
FMCO'09 Proceedings of the 8th international conference on Formal methods for components and objects
SCRATCH: a tool for automatic analysis of dma races
Proceedings of the 16th ACM symposium on Principles and practice of parallel programming
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Strengthening induction-based race checking with lightweight static analysis
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
A halting algorithm to determine the existence of decoder
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Encoding industrial hardware verification problems into effectively propositional logic
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Linear completeness thresholds for bounded model checking
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Relational abstractions for continuous and hybrid systems
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Software verification using k-induction
SAS'11 Proceedings of the 18th international conference on Static analysis
Making software verification tools really work
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Incremental preprocessing methods for use in BMC
Formal Methods in System Design
Benchmarking a model checker for algorithmic improvements and tuning for performance
Formal Methods in System Design
Designing safe, reliable systems using scade
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Abstraction and refinement in model checking
FMCO'05 Proceedings of the 4th international conference on Formal Methods for Components and Objects
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Optimizing bounded model checking for linear hybrid systems
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Property-specific sequential invariant extraction for SAT-based unbounded model checking
Proceedings of the International Conference on Computer-Aided Design
Efficient state space exploration: interleaving stateless and state-based model checking
Proceedings of the International Conference on Computer-Aided Design
Bounded model checking for weak alternating büchi automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Applications of craig interpolants in model checking
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
DiVer: SAT-based model checking platform for verifying large scale systems
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
IC3: where monolithic and incremental meet
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A theory of abstraction for arrays
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Proving ∀µ-calculus properties with SAT-based model checking
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Solving quantified boolean formulas with circuit observability don't cares
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Efficient abstraction refinement in interpolation-based unbounded model checking
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Formal Methods in System Design
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
SAT-solving in CSP trace refinement
Science of Computer Programming
Incremental verification with mode variable invariants in state machines
NFM'12 Proceedings of the 4th international conference on NASA Formal Methods
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Specification and verification of multi-agent systems
ESSLLI'10 Proceedings of the 2010 conference on ESSLLI 2010, and ESSLLI 2011 conference on Lectures on Logic and Computation
On the Magnitude of Completeness Thresholds in Bounded Model Checking
LICS '12 Proceedings of the 2012 27th Annual IEEE/ACM Symposium on Logic in Computer Science
Timed relational abstractions for sampled data control systems
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
SMT-Based induction methods for timed systems
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
SAT-based model checking: interpolation, IC3 and beyond
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Handling unbounded loops with ESBMC 1.20
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SAT: Based bounded strong satisfiability checking of reactive system specifications
ICT-EurAsia'13 Proceedings of the 2013 international conference on Information and Communication Technology
Science of Computer Programming
Using cubes of non-state variables with property directed reachability
Proceedings of the Conference on Design, Automation and Test in Europe
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
Thread-based multi-engine model checking for multicore platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verifying refutations with extended resolution
CADE'13 Proceedings of the 24th international conference on Automated Deduction
Compositional verification of a medical device system
Proceedings of the 2013 ACM SIGAda annual conference on High integrity language technology
Automated reencoding of boolean formulas
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Time-aware relational abstractions for hybrid systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
Observations on formal safety analysis in practice
Science of Computer Programming
Hi-index | 0.00 |
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-solver. We describe some novel induction-based methods, and show how they are related to more standard fixpoint algorithms for invariance checking. We also present preliminary experimental results in the verification of FPGA cores. This demonstrates the practicality of combining a SAT-solver with induction for safety property checking of hardware in a real design flow.