Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
AbsCon: A Prototype to Solve CSPs with Abstraction
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
SyCE: An Integrated Environment for System Design in SystemC
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Redundancy and Don't Cares in Logic Synthesis
IEEE Transactions on Computers
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Bounded model checking of software using SMT solvers instead of SAT solvers
International Journal on Software Tools for Technology Transfer (STTT)
Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Property analysis and design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
SMT techniques for fast predicate abstraction
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Abstraction refinement for bounded model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
sKizzo: a suite to evaluate and certify QBFs
CADE' 20 Proceedings of the 20th international conference on Automated Deduction
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Fault Localization for Property Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analyzing Functional Coverage in Bounded Model Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RobuCheck: a robustness checker for digital circuits
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
| Hi-index | 0.00 |
Due to high computational costs of formal verification on pure Boolean level, proof techniques on the word level, like Satisfiability Modulo Theories (SMT), were proposed. Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress. In this work we present the word level framework WoLFram that enables the development of applications for formal verification of systems independent of the underlying proof technique. The framework is partitioned into an application layer, a core engine and a back-end layer. A wide range of applications is implemented, e.g.~equivalence and property checking including algorithms for coverage/property analysis, debugging and robustness checking. The back-end supports Boolean as well as word level techniques, like SMT and Constraint Solving (CSP). This makes WoLFram a stable backbone for the development and quick evaluation of emerging verification techniques.