Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Symbolic fault tree analysis for reactive systems
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit Reliability Analysis Using Symbolic Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
RobuCheck: a robustness checker for digital circuits
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
| Hi-index | 0.00 |
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tolerance are known. But assessing the fault tolerance of a given circuit is a tough problem. Here, we propose the use of formal methods to assess the robustness of a digital circuit with respect to transient faults. Our formal model uses a fixed bound in time to cope with the complexity of the underlying sequential equivalence check. The result is a lower and an upper bound on the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In experiments the method is evaluated on circuits with different fault detection mechanisms.