Implicit and incremental computation of primes and essential primes of Boolean functions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Symbolic Model Checking
Combining Various Solution Techniques for Dynamic Fault Tree Analysis of Computer Systems
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
The Galileo Fault Tree Analysis Tool
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
The FSAP/NuSMV-SA Safety Analysis Platform
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on Advances in Automated Verification of Critical Systems
Designing safe, reliable systems using scade
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Retrenchment, and the generation of fault trees for static, dynamic and cyclic systems
SAFECOMP'06 Proceedings of the 25th international conference on Computer Safety, Reliability, and Security
Model-based safety analysis of simulink models using SCADE design verifier
SAFECOMP'05 Proceedings of the 24th international conference on Computer Safety, Reliability, and Security
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
From probabilistic counterexamples via causality to fault trees
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Model-based dependability analysis of programmable drug infusion pumps
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
Timed relational abstractions for sampled data control systems
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, which can cause a given top level event, e.g. a system malfunction, to occur. Generating fault trees is particularly critical in the case of reactive systems, as hazards can be the result of complex interactions involving the dynamics of the system and of the faults. Recently, there has been a growing interest in model-based fault tree analysis using formal methods, and in particular symbolic model checking techniques. In this paper we present a broad range of algorithmic strategies for efficient fault tree analysis, based on binary decision diagrams (BDDs). We describe different algorithms encompassing different directions (forward or backward) for reachability analysis, using dynamic cone of influence techniques to optimize the use of the finite state machine of the system, and dynamically pruning of the frontier states. We evaluate the relative performance of the different algorithms on a set of industrial-size test cases.