An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fault-Tolerant Systems
An Analysis Framework for Transient-Error Tolerance
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
New Methods of Concurrent Checking (Frontiers in Electronic Testing)
New Methods of Concurrent Checking (Frontiers in Electronic Testing)
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Verification and Analysis of Self-Checking Properties through ATPG
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complementary Formal Approaches for Dependability Analysis
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Symbolic fault tree analysis for reactive systems
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Verification for fault tolerance of the IBM system z microprocessor
Proceedings of the 47th Design Automation Conference
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Circuit Reliability Analysis Using Symbolic Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective Robustness Analysis Using Bounded Model Checking Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Hardware systems are becoming more and more vulnerable to soft errors caused by radiation or process variations. Design techniques to cope with these problems are built into the system. But how to verify that the final system is as resilient as expected? The paper covers modeling issues related to assessing fault tolerance and reliability. Existing approaches are reviewed that analyze transient faults on the electrical as well as the logical level. Trade-offs regarding resource requirements and quality of results are discussed and the individual advantages are highlighted.