Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
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Evaluating the robustness of digital circuits with respect to soft errors has become an important part of the design flow for many applications. The identification of the most or less critical registers is often necessary, in order to reach the lowest overheads while achieving a given application-level robustness. The goal here is to identify those soft errors actually harmful for the system, not to compute the Soft Error Rate. In this context, we investigate new approaches based on formal techniques to improve design-time robustness evaluations at least for the most critical blocks in a circuit. Preliminary results are shown, focusing on the evaluation of self-healing (or self-repairing) capabilities.