Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Self-stabilization
Self-stabilizing systems in spite of distributed control
Communications of the ACM
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Introduction to Automata Theory, Languages, and Computation (3rd Edition)
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
The good old Davis-Putnam procedure helps counting models
Journal of Artificial Intelligence Research
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Complementary Formal Approaches for Dependability Analysis
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and Mitigating Transient Errors in Logic Circuits
IEEE Transactions on Dependable and Secure Computing
sharpSAT: counting models with advanced component caching and implicit BCP
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
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We propose and investigate a robustness evaluation procedure for sequential circuits subject to particle strikes inducing bit-flips in memory elements. We define a general fault model, a parametric reparation model and quantitative measures reflecting the robustness capability of the circuit with respect to these fault and reparation models. We provide algorithms to compute these metrics and show how they can be interpreted in order to better understand the robustness capability of several circuits (a simple circuit coming from the VIS distribution, circuits from the itc-99 benchmarks and a CAN-Bus interface).