Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
Decomposing a permutation into a conjugated tensor product
ISSAC '97 Proceedings of the 1997 international symposium on Symbolic and algebraic computation
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Introduction to Algorithms
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Improving Gate-Level Simulation of Quantum Circuits
Quantum Information Processing
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logic Circuits Testing for Transient Faults
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Gate-level simulation of quantum circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
PRISM: a tool for automatic verification of probabilistic systems
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Reliable computation by formulas in the presence of noise
IEEE Transactions on Information Theory
Evaluating the reliability of NAND multiplexing with PRISM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Organizing wires for reliability in magnetic QCA
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A probabilistic Boolean logic for energy efficient circuit and system design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Proceedings of the Conference on Design, Automation and Test in Europe
RAG: an efficient reliability analysis of logic circuits on graphics processing units
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate_variables and eliminate_redundant_variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM framework for reliability computation. We further define a susceptibility measure to identify gates whose errors are not well masked. We show that hardening a few gates can significantly improve circuit reliability.