Low power and high performance design challenges in future technologies
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Probabilistic arithmetic and energy efficient embedded signal processing
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Probabilistic system-on-a-chip architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermally-induced soft errors in nanoscale CMOS circuits
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates
IEEE Transactions on Nanotechnology
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
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We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (pbl). By combining the properties of pbl with the properties of noise susceptible cmos devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs.