Thermally-induced soft errors in nanoscale CMOS circuits

Authors:
H. Li;J. Mundy;W. Patterson;D. Kazazis;A. Zaslavsky;R. I. Bahar
Affiliations:
Division of Engineering, Brown University, Providence, RI 02912, USA;Division of Engineering, Brown University, Providence, RI 02912, USA;Division of Engineering, Brown University, Providence, RI 02912, USA;Division of Engineering, Brown University, Providence, RI 02912, USA;Division of Engineering, Brown University, Providence, RI 02912, USA;Division of Engineering, Brown University, Providence, RI 02912, USA
Venue:
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Year:
2007

Citing 0
Cited 5

Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects

CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuits

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices

Proceedings of the 20th symposium on Great lakes symposium on VLSI
A probabilistic Boolean logic for energy efficient circuit and system design

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On pedagogy of nanometric circuit reliability

The Journal of Supercomputing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation character ized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD. The theoretical distribution of transition times from one stable operation point to the other stable operation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days. Monte Carlo simulations are provided to validate the theoretical model and its predictions.