A Markov Random Field Model-Based Approach to Image Interpretation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Markov random field modeling in computer vision
Markov random field modeling in computer vision
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Designing MRF based error correcting circuits for memory elements
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 06
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits
Proceedings of the conference on Design, automation and test in Europe
Thermally-induced soft errors in nanoscale CMOS circuits
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Hi-index | 0.01 |
As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-µm CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 × 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 × 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 µW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design [1].