Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Energy-efficient dynamic circuit design in the presence of crosstalk noise
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Device and circuit simulation of quantum electronic devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel technique to improve noise immunity of CMOS dynamic logic circuits
Proceedings of the 41st annual Design Automation Conference
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Proceedings of the 43rd annual Design Automation Conference
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization for dynamic PLAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient realization of RTD-CMOS logic gates
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Adaptive keeper design for dynamic logic circuits using rate sensing technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
Novel pipeline architectures based on Negative Differential Resistance devices
Microelectronics Journal
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Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.