Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Proceedings of the 43rd annual Design Automation Conference
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip all-digital PV-monitoring architecture for digital IPs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, the VLSI Journal
Domino logic designs for high-performance and leakage-tolerant applications
Integration, the VLSI Journal
Low power wide gates for modern power efficient processors
Integration, the VLSI Journal
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Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This is because to maintain an acceptable noise margin level in deep sub-100 nm technologies, large pMOS keepers must be employed, which generates substantial contention between the keeper and the pull-down network, and hence results in severe loss of performance and high power consumption. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this paper, a novel variation-tolerant keeper architecture is proposed, which is capable of significantly reducing contention and improving performance and power consumption. Using circuit simulations, the overall improved characteristics of the proposed keeper are demonstrated in comparison to those of the traditional as well as several state-of-the-art keepers. The proposed keeper exhibits the lowest delay deviation under different levels of process variations. Also, it is shown that for an eight-input OR gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to the traditional keeper circuit.