Self Calibrating Circuit Design for Variation Tolerant VLSI Systems

Authors:
Chris H. Kim;Steven Hsu;Ram Krishnamurthy;Shekhar Borkar;Kaushik Roy
Affiliations:
University of Minnesota;Intel Corporation, Purdue University;Intel Corporation, Purdue University;Intel Corporation, Purdue University;Intel Corporation, Purdue University
Venue:
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Year:
2005

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Abstract

Increasing leakage current and aggravating process variations are showing impact on dynamic circuit performance and robustness as technology scales into the nanometer regime. This paper describes a self-calibrating process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage enables 10% faster performance, 35% reduction in delay variation, and 5X reduction in the number of robustness failing dies compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. The proposed 6-channel leakage current sensor enables high-resolution on-chip leakage measurements from multiple locations of a die, saving testing cost and realizing both die-to-die and within-die process compensation. Results based on measured leakage data show 1.9-10.2X higher signal-to-noise ratio and reduced sensitivity to supply and P/N skew variations compared to prior leakage sensor designs. The PCD technique with the on-die leakage current sensor is applied to a 2-read, 2-write ported 128x32b register file and a test chip is fabricated in 1.2V, 90nm dual-Vt CMOS process.