Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Characterization of MOS transistor current mismatch
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
On-chip process variations compensation using an analog adaptive body bias (A-ABB)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed sensor is 2.3× better than the previous sensor reported in the literature which utilizes above-threshold operation. To further improve the sensitivity of the proposed sensor, an amplifier stage working in the sub-threshold region is designed. This enables 4× additional increase in sensitivity. A test-chip containing an array of 128 PMOS and 128 NMOS devices has been fabricated in 65-nm bulk CMOS process technology. A total of 28 dies across the wafer have been fully characterized and the random threshold voltage variations are reported here.