Characterization of MOS transistor current mismatch

Authors:
H. Klimach;A. Arnaud;M. C. Schneider;C. Galup-Montoro
Affiliations:
Universidade Federal de Santa Catarina, Florianopolis - Brazil;Universidad de la República, Montevideo - Uruguay;Universidade Federal de Santa Catarina, Florianopolis - Brazil;Universidade Federal de Santa Catarina, Florianopolis - Brazil
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

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Abstract

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, and allows the assessment of mismatch from process and geometric parameters.