Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Power-aware partitioned cache architectures
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Morphable Cache Architectures: Potential Benefits
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Energy-efficient instruction cache using page-based placement
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
An energy saving strategy based on adaptive loop parallelization
Proceedings of the 39th annual Design Automation Conference
Automatic data migration for reducing energy consumption in multi-bank memory systems
Proceedings of the 39th annual Design Automation Conference
Exploiting shared scratch pad memory space in embedded multiprocessor systems
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Select-free instruction scheduling logic
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Tuning garbage collection for reducing memory system energy in an embedded java environment
ACM Transactions on Embedded Computing Systems (TECS)
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
ACM Transactions on Embedded Computing Systems (TECS)
Partitioned instruction cache architecture for energy efficiency
ACM Transactions on Embedded Computing Systems (TECS)
Designing Energy-Efficient Software
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Adaptive Garbage Collection for Battery-Operated Environments
Proceedings of the 2nd Java Virtual Machine Research and Technology Symposium
Optimization and control of VDD and VTH for low-power, high-speed CMOS design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Energy savings through compression in embedded Java environments
Proceedings of the tenth international symposium on Hardware/software codesign
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A compiler approach for reducing data cache energy
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Test Methodology for the McKinley Processor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Vertigo: automatic performance-setting for Linux
ACM SIGOPS Operating Systems Review - OSDI '02: Proceedings of the 5th symposium on Operating systems design and implementation
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
A clock delayed sleep mode domino logic for wide dynamic OR gate
Proceedings of the 2003 international symposium on Low power electronics and design
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Proceedings of the 2003 international symposium on Low power electronics and design
Array Regrouping and Its Use in Compiling Data-Intensive Embedded Applications
IEEE Transactions on Computers
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling compiler-enabled and conventional memory accessing for energy efficiency
ACM Transactions on Computer Systems (TOCS)
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
A trace-based binary compilation framework for energy-aware computing
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-optimal pipelining in deep submicron technology
Proceedings of the 2004 international symposium on Low power electronics and design
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
Resistive Power in CMOS Circuits
Analog Integrated Circuits and Signal Processing
Adaptive supply voltage technique for low swing interconnects
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Runtime Code Parallelization for On-Chip Multiprocessors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical Analysis of Clock Skew Variation in H-Tree Structure
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Noise-tolerant high fan-in dynamic CMOS circuit design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Energy management in software-controlled multi-level memory hierarchies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A high speed and leakage-tolerant domino logic for high fan-in gates
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Speculative Control Scheme for an Energy-Efficient Banked Register File
IEEE Transactions on Computers
Vertigo: automatic performance-setting for Linux
OSDI '02 Proceedings of the 5th symposium on Operating systems design and implementationCopyright restrictions prevent ACM from being able to make the PDFs for this conference available for downloading
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Explaining the gap between ASIC and custom power: a custom perspective
Proceedings of the 42nd annual Design Automation Conference
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
Reducing data cache leakage energy using a compiler-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Banked scratch-pad memory management for reducing leakage energy consumption
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compiler-directed high-level energy estimation and optimization
ACM Transactions on Embedded Computing Systems (TECS)
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Reducing leakage power in instruction cache using WDC for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-leakage SRAM Design with Dual V_t Transistors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Towards formal probabilistic power-performance design space exploration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
CDMA/FDMA-interconnects for future ULSI communications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low power synthesis of dynamic logic circuits using fine-grained clock gating
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing dynamic and leakage energy in VLIW architectures
ACM Transactions on Embedded Computing Systems (TECS)
Reliability modeling and management in dynamic microprocessor-based systems
Proceedings of the 43rd annual Design Automation Conference
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trace-based leakage energy optimisations at link time
Journal of Systems Architecture: the EUROMICRO Journal
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
Improvement of power distribution network using correlation-based regression analysis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exploiting loop behavior for data cache leakage reduction
Journal of Embedded Computing - Cache exploitation in embedded systems
A cache design for high performance embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Proceedings of the conference on Design, automation and test in Europe
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An energy-aware framework for dynamic software management in mobile computing systems
ACM Transactions on Embedded Computing Systems (TECS)
Electronic Notes in Theoretical Computer Science (ENTCS)
Stress aware layout optimization
Proceedings of the 2008 international symposium on Physical design
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
A robust, fast pulsed flip-flop design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power reduction using stress-enhanced layouts
Proceedings of the 45th annual Design Automation Conference
Capturing and optimizing the interactions between prefetching and cache line turnoff
Microprocessors & Microsystems
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-speed low-power FinFET based domino logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Multi-mechanism reliability modeling and management in dynamic systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
A dual-edge triggered phase detector for fast-lock DLL
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive circuit block model for power supply noise analysis of low power system-an-chip
SOC'09 Proceedings of the 11th international conference on System-on-chip
Compiler-directed dynamic voltage scaling using program phases
HiPC'07 Proceedings of the 14th international conference on High performance computing
Accurate estimation of vector dependent leakage power in the presence of process variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-situ characterization and extraction of SRAM variability
Proceedings of the 47th Design Automation Conference
Clock network design for ultra-low power applications
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
HotPower'08 Proceedings of the 2008 conference on Power aware computing and systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip NBTI sensor for measuring pMOS threshold voltage degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of sequential elements for low power clocking system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating strategies on GPUs
ACM Transactions on Architecture and Code Optimization (TACO)
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Energy consumption in RC tree circuits with exponential inputs: an analytical model
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Coupled power and thermal simulation with active cooling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Body bias generator for leakage power reduction of low-voltage digital logic circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Compile-Time energy optimization for parallel applications in on-chip multiprocessors
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part II
mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices
Proceedings of the 49th Annual Design Automation Conference
Mathematical model of stored logic based computation
Mathematical and Computer Modelling: An International Journal
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits
Journal of Signal Processing Systems
A novel and improved design of a ternary CNTFET-based cell
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Design of low energy, high performance synchronous and asynchronous 64-point FFT
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage energy estimates for HPC applications
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
Microprocessors & Microsystems
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From the Publisher:This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world聮s leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.