Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Behavioral level dual-Vth design for reduced leakage power with thermal awareness
Proceedings of the Conference on Design, Automation and Test in Europe
Low power asynchronous circuit back-end design flow
Microelectronics Journal
Low power and high speed multi threshold voltage interface circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1V processes. Rules of thumb are developed for optimal Vdd's and Vth's to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the total power savings is significantly greater than previously anticipated. We describe the impact of level conversion delays and highlight the tradeoff between power savings and critical path count.