Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Low-power circuits using dynamic threshold devices
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Dependability Analysis of Nano-scale FinFET circuits
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
FinFETs for nanoscale CMOS digital integrated circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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According to Moore's law, the number of transistors in a chip doubles every 18 months. The increased transistor-count leads to increased power density. Thus, in modern circuits, power efficiency is a central determinant of circuit efficiency. With scaling, leakage power accounts for an increasingly larger portion of the total power consumption in deep submicron technologies (40%). FinFET technology has been proposed as a promising alternative to deep submicron bulk CMOS technology, because of its better scalability, short-channel characteristics, and ability to suppress leakage current and mitigate device-to-device variability when compared to bulk CMOS. The subthreshold slope of a FinFET is approximately 60mV which is close to ideal. In this article, we propose a methodology for low-power FinFET based circuit synthesis. A mechanism called TCMS (Threshold Control through Multiple Supply Voltages) was previously proposed for improving the power efficiency of FinFET based global interconnects. We propose a significant generalization of TCMS to the design of any logic circuit. This scheme represents a significant divergence from the conventional multiple supply voltage schemes considered in the past. It also obviates the need for voltage level-converters. We employ accurate delay and power estimates using table look-up methods based on HSPICE simulations for supply voltage and threshold voltage optimization. Experimental results demonstrate that TCMS can provide power savings of 67.6% and device area savings of 65.2% under relaxed delay constraints. Two other variants of TCMS are also proposed that yield similar benefits. We compare our scheme to extended cluster voltage scaling (ECVS), a popular dual-Vdd scheme presented in the literature. ECVS makes use of voltage level-converters. Even when it is assumed that these level-converters have zero delay, thus significantly favoring ECVS in time-constrained power optimization, TCMS still outperforms ECVS.