Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Authors:
Abdulkadir Utku Diril;Yuvraj Singh Dhillon;Abhijit Chatterjee;Adit D. Singh
Affiliations:
Nvidia Corporation, Santa Clara, CA and Georgia Institute of Technology, Atlanta, GA;Intel Corporation, Hillsboro, OR and Georgia Institute of Technology, Atlanta, GA;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;Department of Electrical Engineering, Auburn University, Auburn, AL
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nmtechnology and 17% when 70-nmtechnology is used.