Enhanced clustered voltage scaling for low power

Authors:
Monica Donno;Luca Macchiarulo;Alberto Macii;Enrico Macii;Massimo Poncino
Affiliations:
Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

Citing 5
Cited 1

Clustered voltage scaling technique for low-power design

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Energy minimization using multiple supply voltages

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Energy minimization using multiple supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Provably good algorithm for low power consumption with dual supply voltages

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

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Abstract

This paper presents a voltage scaling approach that is based on an enhanced variant of clustered voltage scaling originally proposed by Usami and Horowitz ([1]) The results show that subtituting the original depth first strategy with a breadth first one results in improved speed and quality of results. Data are validated through power and timing analysis performed with a commercial tool.