A reconfigurable dual output low power digital PWM power converter
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Synthesis of low power CMOS VLSI circuits using dual supply voltages
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Provably good algorithm for low power consumption with dual supply voltages
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
LEneS: task scheduling for low-energy systems using variable supply voltage processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low-power technology mapping for mixed-swing logic
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Enhanced clustered voltage scaling for low power
Proceedings of the 12th ACM Great Lakes symposium on VLSI
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An optimal voltage synthesis technique for a power-efficient satellite application
Proceedings of the 39th annual Design Automation Conference
What is the limit of energy saving by dynamic voltage scaling?
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Optimal voltage allocation techniques for dynamically variable voltage processors
Proceedings of the 40th annual Design Automation Conference
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Multivoltage scheduling with voltage-partitioned variable storage
Proceedings of the 2003 international symposium on Low power electronics and design
Voltage scheduling under unpredictabilities: a risk management paradigm
Proceedings of the 2003 international symposium on Low power electronics and design
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
IEEE Transactions on Computers
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An approach for reducing dynamic power consumption in synchronous sequential digital designs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low-power dual Vth pseudo dual Vdd domino circuits
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimal voltage allocation techniques for dynamically variable voltage processors
ACM Transactions on Embedded Computing Systems (TECS)
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages
IEEE Transactions on Computers
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Voltage scheduling under unpredictabilities: a risk management paradigm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages
The Journal of Supercomputing
Low-power domino circuits using NMOS pull-up on off-critical paths
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing dynamic and leakage energy in VLIW architectures
ACM Transactions on Embedded Computing Systems (TECS)
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
Integration, the VLSI Journal
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multiple voltage synthesis scheme for low power design under timing and resource constraints
Integrated Computer-Aided Engineering
Digital Circuit Optimization via Geometric Programming
Operations Research
The Journal of Supercomputing
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Power optimization for simultaneous scheduling and partitioning with multiple voltages
MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WSEAS Transactions on Signal Processing
Multi-voltage floorplan design with optimal voltage assignment
Proceedings of the 2009 international symposium on Physical design
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
A 200-mA, 93% peak power efficiency, single-inductor, dual-output DC---DC buck converter
Analog Integrated Circuits and Signal Processing
Multivoltage multifrequency low-energy synthesis for functionally pipelined datapath
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enabling power-efficient DVFS operations on silicon
IEEE Circuits and Systems Magazine
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high efficiency 4-output single inductor DC---DC buck converter with self boosted snubber
Analog Integrated Circuits and Signal Processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An approach to energy-error tradeoffs in approximate ripple carry adders
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
The approximation scheme for peak power driven voltage partitioning
Proceedings of the International Conference on Computer-Aided Design
Memory access aware on-line voltage control for performance and energy optimization
Proceedings of the International Conference on Computer-Aided Design
Temperature aware datapath scheduling
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A Heuristic for reducing dynamic power dissipation in clocked sequential designs
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power timing closure methodology for ultra-low voltage designs
Proceedings of the International Conference on Computer-Aided Design
Analog Integrated Circuits and Signal Processing
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We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a supply voltage level (selected from a fixed and known number of voltage levels) to each operation in a data flow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using three supply voltage levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single supply voltage level.