Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Scheduling with multiple voltages
Integration, the VLSI Journal
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gate-level design exploiting dual supply voltages for power-driven applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of low power CMOS VLSI circuits using dual supply voltages
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Provably good algorithm for low power consumption with dual supply voltages
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Power reduction by simultaneous voltage scaling and gate sizing
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical design with multiple on-chip voltages
Proceedings of the 2002 international symposium on Physical design
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
Proceedings of the 39th annual Design Automation Conference
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Voltage scheduling under unpredictabilities: a risk management paradigm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
Digital Circuit Optimization via Geometric Programming
Operations Research
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Postplacement voltage assignment under performance constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture support for disciplined approximate programming
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Slack budgeting and slack to length converting for multi-bit flip-flop merging
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present an approach for applying two supply voltges to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of slacks. Based on this strategy, the power reductionis translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total poer saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared tot he average power improvement of about 7% bgy gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization.