Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling with multiple voltages
Integration, the VLSI Journal
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of convergence properties of a stochastic evolution algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work addresses the problem of low power design in high-level synthesis in the scenario of the resources operating at multiple voltages. The problem of resource-and-latency constrained scheduling is tackled and a novel methodology for scheduling as well as design space exploration is proposed. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal parallelism of power hungry operators in resource-constrained/time-constrained designs. A novel scheme is devised for recognizing the "zones" of parallel operators that result in maximal power savings when rescheduled to lower voltages. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in O(n2), where n is the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resource-and-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3-5% of the integer-linear-programming based (i.e., exponential-time-complexity) method. The details and the analysis of the results on the standard high-level synthesis benchmarks are provided. Further, analysis of schedules is given for considering generation of control signals for switching the resources. This is the first work to consider such analysis besides proposing an efficient algorithm.