Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A multiple clocking scheme for low power RTL design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Boolean techniques for low power driven re-synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
System partitioning to maximize sleep time
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power optimization in disk-based real-time application specific systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Low-power adaptive filter architectures via strength reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Low power, testable dual edge triggered flip-flops
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Low power high level synthesis by increasing data correlation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Dynamic algorithm transformation (DAT) for low-power adaptive signal processing
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tools and methodologies for low power design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Potential-driven statistical ordering of transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power-conscious high level synthesis using loop folding
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 1997 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A methodology for guided behavioral-level optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introducing redundant computations in a behavior for reducing BIST resources
DAC '98 Proceedings of the 35th annual Design Automation Conference
Decorrelating (DECOR) transformations for low-power adaptive filters
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The logarithmic number system for strength reduction in adaptive filtering
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power efficient mediaprocessors: design space exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power macro-models for DSP blocks with application to high-level synthesis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Power optimization using divide-and-conquer techniques for minimization of the number of operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A methodology and algorithms for the design of hard real-time multitasking ASICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
Journal of VLSI Signal Processing Systems
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Proceedings of the 37th Annual Design Automation Conference
Influence of compiler optimizations on system power
Proceedings of the 37th Annual Design Automation Conference
Synthesis-for-testability of controller-datapath pairs that use gated clocks
Proceedings of the 37th Annual Design Automation Conference
Throughput optimization of general non-linear computations
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retiming-based factorization for sequential logic optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of VLSI Signal Processing Systems
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Input space adaptive design: a high-level methodology for energy and performance optimization
Proceedings of the 38th annual Design Automation Conference
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Influence of compiler optimizations on system power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Efficient global register allocation for minimizing energy consumption
ACM SIGPLAN Notices
Energy-conscious compilation based on voltage scaling
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Energy estimation of nested loop programs
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
An Integrated CAD Environment for Low-Power Design
IEEE Design & Test
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
PACT HDL: a compiler targeting ASICS and FPGAS with power and performance optimizations
Power aware computing
Compiler optimizations for low power systems
Power aware computing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Accurate high level datapath power estimation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction Scheduling for Low Power
Journal of VLSI Signal Processing Systems
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
Power minimization in QoS sensitive systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cycle-Accurate Energy Measurement and Characterization of FPGAs
Analog Integrated Circuits and Signal Processing
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
Register-Transfer Level Transformations for Low-Power Data-Paths
Integrated Computer-Aided Engineering
Network Flow Approach to Data Regeneration for Low Energy Embedded System Synthesis
Integrated Computer-Aided Engineering
Techniques for maintaining connectivity in wireless ad-hoc networks under energy constraints
ACM Transactions on Embedded Computing Systems (TECS)
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Proceedings of the 45th annual Design Automation Conference
A design automation and power estimation flow for RFID systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WSEAS Transactions on Signal Processing
VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 × 4 MIMO-OFDM Receiver
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Scheduling with multiple voltages
Integration, the VLSI Journal
Want to save energy?: put intelligence into systems
CSECS'09 Proceedings of the 8th WSEAS International Conference on Circuits, systems, electronics, control & signal processing
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting finite precision information to guide data-flow mapping
Proceedings of the 47th Design Automation Conference
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
Low power scheduling of DAGs to minimize finish times
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Concurrency and Computation: Practice & Experience
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
Low-energy encryption for medical devices: security adds an extra design dimension
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area