Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low power pipelining of linear systems: a common operand centric approach
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Multiple voltage and frequency scheduling for power minimization
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
GlitchLess: an active glitch minimization technique for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Pipelining with common operands for power-efficient linear systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a transformation technique, called power-consciousloop folding is proposed for high level synthesis of alow power system. Our work is focused on reducing the powerconsumed by functional units through the decrease of switchingactivity in a data path dominated circuit containing loops. Thetransformation algorithm has been implemented and integratedinto a high level synthesis system for experiments. In ourexperiments, we could achieve power reduction of up to 50% forcircuits dominated by functional units.