Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Power-conscious high level synthesis using loop folding
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Multiple voltage and frequency scheduling for power minimization
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipelining with common operands for power-efficient linear systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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