Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Code generation schema for modulo scheduled loops
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Lifetime-sensitive modulo scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic Loop Scheduling for Applications with Uncertain Execution Time
IEEE Transactions on Computers
Low power synthesis of sum-of-products computation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power-aware modulo scheduling for high-performance VLIW processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power pipelining of linear systems: a common operand centric approach
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Efficient instruction-level optimization methodology for low-power embedded systems
Proceedings of the 14th international symposium on Systems synthesis
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
IEEE Transactions on Parallel and Distributed Systems
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction Scheduling Based on Energy and Performance Constraints
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Scheduling Strategies for Master-Slave Tasking on Heterogeneous Processor Platforms
IEEE Transactions on Parallel and Distributed Systems
Efficient Assignment and Scheduling for Heterogeneous DSP Systems
IEEE Transactions on Parallel and Distributed Systems
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction.