System level optimization and design space exploration for low power
Proceedings of the 14th international symposium on Systems synthesis
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Effective graph theoretic techniques for the generalized low power binding problem
Proceedings of the 2003 international symposium on Low power electronics and design
A low power scheduler using game theory
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Predictable design of low power systems by pre-implementation estimation and optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Voltage scheduling under unpredictabilities: a risk management paradigm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors
International Journal of High Performance Computing and Networking
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UVM-based verification methodology for RFID-enabled smart-sensor systems
Analog Integrated Circuits and Signal Processing
Microprocessors & Microsystems
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In this paper, we present an approach for the calculation of lower and upper bounds on the power consumption of data path resources like functional units, registers, I/O ports, and busses from scheduled data flow graphs executing a specified input data stream. The low power allocation and binding problem is formulated. First, it is shown that this problem without constraining the number of resources can be relaxed to the bipartite weighted matching problem which is solvable in O(n)/sup 3/. n is the number of arithmetic operations, variables, I/O-access or bus-access operations which have to be bound to data path resources. In a second step we demonstrate that the relaxation can be efficiently extended by including Lagrange multipliers in the problem formulation to handle a resource constraint. The estimated bounds take into account the effects of resource sharing. The technique can be used, for example, to prune the design space in high-level synthesis for low power before the allocation and binding of the resources. The application of the technique on benchmarks with real application input data shows the tightness of the bounds.