Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-Power CMOS Design
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Universal verification methodology (UVM) is a standardized methodology for verifying integrated circuit designs. In this contribution, we present a UVM-based verification methodology for verifying mixed-signal smart-sensor systems. Our approach permits the validation of system functionality before implementation and also to verify the implementation on various levels of abstraction. The model-based verification approach enables to build a scalable and reusable framework, in which assertions and constrained-random stimuli are used to monitor and also to verify mixed-signal-system behavior automatically. A comprehensive example of an radio-frequency identification-based smart-sensor mixed-signal system used for bioanalytical applications is presented. Along with the designed UVM test bench architecture, we describe a novel solution for estimating the power consumption of the digital sub-system using application-specific random-activity patterns generated during UVM test bench runs (Neumann et al., Synthesis Modelling Analysis and Simulation Methods and Application to Circuit Design, SMACD, 2012).