Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Statistical sampling and regression analysis for RT-level power evaluation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Cycle-accurate macro-models for RT-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Characterization-free behavioral power modeling
Proceedings of the conference on Design, automation and test in Europe
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Proceedings of the 14th international symposium on Systems synthesis
Low-Power CMOS Design
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C-based SoC design flow and EDA tools: an ASIC and system vendor perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An information-theoretic model for adaptive side-channel attacks
Proceedings of the 14th ACM conference on Computer and communications security
Automatically deriving information-theoretic bounds for adaptive side-channel attacks
Journal of Computer Security
UVM-based verification methodology for RFID-enabled smart-sensor systems
Analog Integrated Circuits and Signal Processing
Microprocessors & Microsystems
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Cycle-accurate functional descriptions (CAFD) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent increase in simulation efficiency of cycle-based functional simulation. Currently, most approaches to hardware power estimation operate at the register-transfer level (RTL), or lower levels of design abstraction. Attempts at power estimation for functional descriptions have suffered from poor accuracy because the design decisions performed during their synthesis lead to an unavoidable, large uncertainty in any power estimate that is based solely on the functional description. We propose a methodology for CAFD power estimation that combines the accuracy achieved by power estimation at the structural RTL with the efficiency of cycle-accurate functional simulation. We achieve this goal by viewing a CAFD as an abstraction of a specific, known RTL implementation that is synthesized from it. We identify correlations between a CAFD and its RTL implementation, and "back-annotate" information into the CAFD solely for the purpose of power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components, and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in our methodology by simply co-simulating the RTL-aware CAFD with a simulatable power model library that contains power macro-models for each RTL component. We present techniques to further improve the speed of CAFD power estimation, through the use of control state-based adaptive power sampling. We have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 million gates) demonstrate that the proposed methodology achieves accuracy very close to RTL power estimation with two-to-three orders of magnitude speedup in estimation times.