Adaptive signal processing
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The design and implementation of PowerMill
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Distributed EDA Tool Integration: The PPP Paradigm
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Regression Models for Behavioral Power Estimation
Integrated Computer-Aided Engineering
The petrol approach to high-level power estimation
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Characterization-free behavioral power modeling
Proceedings of the conference on Design, automation and test in Europe
A new method for constructing IP level power model based on power sensitivity
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work we propose an effective solution to the main challenges of behavioral power modeling: the generation of models for the power dissipation of technology-independent soft macros and the strong dependence of power from input pattern statistics. Our methodology is based on a fast characterization performed by simulating the gate-level implementation of instances of soft macros within the behavioral description of the complete design. Once characterization has been completed, the backannotated behavioral model replaces the gate-level representation, thus allowing fast but accurate power estimates in a fully behavioral context. Our power characterization procedure is a very efficient process that can be easily embedded in synthesis-based design flows. No additional effort is required from the designer, since power characterization merges seamlessly with a natural top-down design methodology with iterative improvement. After characterization, the behavioral power simulation produces accurate average and instantaneous pourer estimates (with errors around 7% and 25%, respectively, from accurate gate-level power simulation).