Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A power estimation framework for designing low power portable video applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lower and upper bounds on the switching activity in scheduled data flow graphs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
System level optimization and design space exploration for low power
Proceedings of the 14th international symposium on Systems synthesis
Lower bound estimation for low power high-level synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Memory power models for multilevel power estimation and optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel modeling techniques for RTL power estimation
Proceedings of the 2002 international symposium on Low power electronics and design
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
An Improved Power Macro-Model for Arithmetic Datapath Components
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Challenges for architectural level power modeling
Power aware computing
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs
Proceedings of the 2006 international symposium on Low power electronics and design
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Analytical High-Level Power Model for LUT-Based Components
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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