Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Regression-based RTL power models for controllers
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Clustered Table-Based Macromodels for RTL Power Estimation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Lookup Table Power Macro-Models for Behavioral Library Components
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for RTL power estimation of combinational and sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Markov chain sequence generator for power macromodeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-Accuracy Power and Performance Transaction-Level Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Register transfer level (RTL) power macromodeling is a mature research topic with a variety of equation and table-based approaches. Despite its maturity, macromodeling is not yet widely accepted as a de facto industrial standard for power estimation at the RT level. Each approach has many variants depending upon the parameters chosen to capture power variation. Every macromodeling technique has some intrinsic limitation affecting either its performance or its accuracy. Therefore, alternative macromodeling methods can be envisaged as part of a power modeling toolkit from which multiple models for a given component could be exploited so as to reduce the estimation errors resulting from conventional single-model approaches. This paper describes two different approaches for a new multi-model power estimation engine. The first one selects the macromodeling technique that leads to the least estimation error, for a given system component, depending on the properties of its input-vector stream. A proper selection function is built after component characterization and used during estimation. Though simple, this approach has revealed a substantial improvement in estimation accuracy. The second one builds a power estimate function that captures the correlation between individual macromodel estimates and input-stream properties. Experimental results show that our multi-model engine improves the robustness of power analysis with negligible usage overhead. Accuracy becomes seven times better on average, as compared to conventional single-model estimators, while the overall maximum estimation error is divided by 9.