ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
A power modeling and characterization method for macrocells using structure information
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Cycle-accurate simulation of energy consumption in embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power optimization using divide-and-conquer techniques for minimization of the number of operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Regression-based RTL power models for controllers
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Low power pipelining of linear systems: a common operand centric approach
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Lower bound estimation for low power high-level synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Source code optimization and profiling of energy consumption in embedded systems
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient global register allocation for minimizing energy consumption
ACM SIGPLAN Notices
Power estimation of embedded systems: a hardware/software codesign approach
Readings in hardware/software co-design
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
RTL Estimation of Steering Logic Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Challenges for architectural level power modeling
Power aware computing
Probabilistic Bottom-Up RTL Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
SEA: fast power estimation for micro-architectures
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 46th Annual Design Automation Conference
High-radix residue arithmetic bases for low-power DSP systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Pipelining with common operands for power-efficient linear systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criterion. As such there is a growing need for tools that can accurately predict power consumption early in the design process, many high-level power analysis models do not adequately model activity, however, leading to inaccurate results. This paper describes an activity-sensitive power analysis strategy for datapath, memory, control path, and interconnect elements. Since datapath and memory modeling has been described in a previous publication, this paper focuses mainly on a new Activity-Based Control (ABC) model and on a hierarchical interconnect analysis strategy that enables estimates of chip area as well as power consumption. Architecture-level estimates are compared to switch-level measurements based on net lists extracted from the layouts of three chips: a digital filter, a global controller, and a microprocessor. The average power estimation error is about 9% with a standard deviation of 10%, and the area estimates err on average by 14% with a standard deviation of 6%