Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power dissipation due to the steering logic, that is, the multiplexer network and the interconnect, can usually account for a significant fraction of the total power budget. In this work, we present RTL power models for these two types of architectural elements. The multiplexer model leverages existing scalable models, and can be used for special complex types with re-configurable numbers of data bits and ways. The interconnect model is obtained by empirically relating capacitance to circuit area, that is either estimated by means of statistical models or extracted from back-annotation information available at the gate level.