Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Connectivity Models for Optoelectronic Computing Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
RTL Estimation of Steering Logic Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
IEEE Transactions on Computers
Hybrid Pipeline Structure for Self-Organizing Learning Array
ISNN '07 Proceedings of the 4th international symposium on Neural Networks: Part II--Advances in Neural Networks
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Information flow and interconnections in computing: extensions and applications of Rent's rule
Journal of Parallel and Distributed Computing
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the asymptotic costs of multiplexer-based reconfigurability
Proceedings of the 49th Annual Design Automation Conference
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
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It is shown from simple theoretical considerations that the distribution fk of wire lengths for a good two-dimensional placement on a square Manhattan grid should be of the form fk = g/kγ (1 ≤ k ≤ L) and fk ≅ 0 (k L), where γ is related to the Rent partitioning exponent p by the equation 2p + γ ≅ 3. Three placements were investigated and the distribution functions for wire length were found to follow the above relationships.