Building IBM: shaping an industry and its technology
Building IBM: shaping an industry and its technology
Wirelength estimation based on rent exponents of partitioning and placement
Proceedings of the 2001 international workshop on System-level interconnect prediction
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A priori wire length distribution models with multiterminal nets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
The IBM eServer z990 microprocessor
IBM Journal of Research and Development
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Adaptable wire-length distribution with tunable occupation probability
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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IBM Journal of Research and Development
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Roadmap towards ultimately-efficient zeta-scale datacenters
Proceedings of the Conference on Design, Automation and Test in Europe
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Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rent's memos is needed for today's components. We have obtained copies of Rent's two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and the IBM 1410 computers. We have studied these memos carefully in order to understand Rent's original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rent's memos suitable for today's computer components. The purpose of this paper is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this paper, we will: 1) describe the contents of the memos and Rent's method; 2) provide an historically-equivalent interpretation of Rent's memos for today's computer components; and 3) apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 micro-processor. In this paper, we will showthat this new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.